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Solution
Q.35 Correct
Q.35 In-correct
Q.35 Unattempt

Consider a pipelined processor operating at 2 GHZ with 5 stages, Instruction fetch (IF), Instruction decode (ID), Execute (EX), Memory access (MEM), and write back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. The EX takes one cycle for ADD and SUB, three cycles for MUL, two cycles for DIV Instruction.

Consider the following instructions:

l1 : ADD R1, R2, R3 ;           R1 ← R2 + R3

l2 : SUB R3, R2, R1 ;          R3 ← R2 - R1

I3 : MUL R4, R1, R2 ;           R4 ← R5 * R2

l4 : DIV R3, R4, R3 ;                      R3 ← R4 / R3 

Find, the number of true data dependences in the above code and the execution time using operand forwarding technique respectively is______.

Consider a pipelined processor operating at 2 GHZ with 5 stages, Instruction fetch (IF), Instruction decode (ID), Execute (EX), Memory access (MEM), and write back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. The EX takes one cycle for ADD and SUB, three cycles for MUL, two cycles for DIV Instruction.

Consider the following instructions:

l1 : ADD R1, R2, R3 ;           R1 ← R2 + R3

l2 : SUB R3, R2, R1 ;          R3 ← R2 - R1

I3 : MUL R4, R1, R2 ;           R4 ← R5 * R2

l4 : DIV R3, R4, R3 ;                      R3 ← R4 / R3 

Find, the number of true data dependences in the above code and the execution time using operand forwarding technique respectively is______.

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