Consider the complex valued function \(\rm f(z) = 2z^3 + b |z|^3\) where \(\rm z\) is a complex variable.

As \(\rm x\) varies from \(\rm −1\ to \ +3\), which one of the following describes the behaviour of the function \(\rm f(x) = x^3 – 3x^2 + 1\)?

In the circuit shown below, V_S is a constant voltage source and I_L is a constant current load.

The value of \(\rm I_L\) that maximizes the power absorbed by the constant current load is

The switch has been in position 1 for a long time and abruptly changes to position 2 at t = 0.

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If time \(\rm t\) is in seconds, the capacitor voltage \(\rm V_C\) (in volts) for \(\rm t > 0\) is given by

The figure shows an RLC circuit with a sinusoidal current source:

At resonance, the ratio |𝐈_𝐋|/|𝐈_𝐑|, i.e., the ratio of the magnitudes of the inductor current phasor and the resistor current phasor, is ________

The z-parameter matrix for the two-port network shown is

\(\left[ {\begin{array}{*{20}{c}} {2{\rm{jω }}}&{{\rm{jω }}}\\ {{\rm{jω }}}&{3 + 2{\rm{jω }}} \end{array}} \right]\)

where the entries are in Ω. Suppose Z_b(jω) = R_b + jω.

Then the value of R_b (in Ω) equals ________.

Assume that the diode in the figure has V_on = 0.7 V, but is otherwise ideal.

The magnitude of the current i₂ (in mA) is equal to ________

Resistor R₁ in the circuit below has been adjusted such that I₁ = 1 mA. The bipolar transistors Q₁ and Q₂ are perfectly matched and have very high current gain, so their base currents are negligible. The supply voltage V_CC is 6 V. The thermal voltage kT/q is 26 mV.

The value of R₂ (in Ω) for which I₂ = 100 μA is ________

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst-case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst-case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R = 10 kΩ, and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4, and D5 are initialized with logic values 0, 1, 0, 1, and 0 respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while C_in is the input carry and C_out is the output carry. A and B  are to be used as the select bits with A being the more significant select bit.

The response of the system \({\rm{G}}\left( {\rm{s}} \right) = \frac{{{\rm{s}} - 2}}{{\left( {{\rm{s}} + 1} \right)\left( {{\rm{s}} + 3} \right)}}\) to the unit step input \(\rm u(t)\) is \(\rm y(t)\).

Light from free space is incident at an angle θ₁to the normal of the facet of a step-index large core optical fibre. The core and cladding refractive indices are n₁ = 1.5 and n₂ = 1.4, respectively.

The maximum value of θ₁ (in degrees) for which the incident light will be guided in the core of the fibre is ________.

The ordinary differential equation \(\frac{{{\rm{dy}}}}{{{\rm{dt}}}} = - 3{\rm{x}} + {\rm{}}2,{\rm{with\ x}}\left( 0 \right){\rm{\;}} = {\rm{\;}}1\)

Two random variables \(\rm X\) and \(\rm Y\) are distributed according to

\({\rm{f_{X,{{\rm{Y}}}}}{\left( {{\rm{x}},{\rm{y}}} \right)}} = \left\{ {\begin{array}{*{20}{c}} {\left( {{\rm{x}} + {\rm{y}}} \right)}&{{\rm{0}} \le {\rm{x}} \le 1}&{0 \le {\rm{y}} \le 1}\\ {0,}&{{\rm{otherwise}}.}&{\rm{\;}} \end{array}} \right.\)

The matrix \({\rm{A}} = \left[ {\begin{array}{*{20}{c}} {\rm{a}}&0&3&7\\ 2&5&1&3\\ 0&0&2&4\\ 0&0&0&{\rm{b}} \end{array}} \right]\) has \(\rm det(A) = 100\) and \(\rm trace(A) = 14\).

In the given circuit, each resistor has a value equal to 1 Ω.

What is the equivalent resistance across the terminals 𝑎 and 𝑏?

In the circuit shown in the figure, the magnitude of the current (in amperes) through R2 is ________.

The Discrete Fourier Transform (DFT) of the 4-point sequence

\(\rm x[n] = \{x[0], x[1], x[2], x[3]\} = \{3, 2, 3, 4\}\) is

\(\rm X[k] = \{X[0], X[1], X[2], X[3]\} = \{12, 2j, 0, −2j\}\).

If \(\rm X_1[k]\) is the DFT of the 12-point sequence \(\rm x_1[n] = \{3, 0, 0, 2, 0, 0, 3, 0, 0, 4, 0, 0\}\), the value of \(\left| {\frac{{{{\rm{X}}_1}\left[ 8 \right]}}{{{{\rm{X}}_1{\left[ {11} \right]}}_{\rm{\;}}}}} \right|\) is ________

The switch S in the circuit shown has been closed for a long time. It is opened at time t = 0 and remains open after that. Assume that the diode has zero reverse current and zero forward voltage drop.

The steady-state magnitude of the capacitor voltage V_c (in Volts) is ________.

A voltage \(\rm V_G\) is applied across a MOS capacitor with metal gate and p-type silicon substrate at \(\rm T=300 \ K\). The inversion carrier density (in number of carriers per unit area) for \(\rm V_G = 0.8 \ V\) is \(\rm 2 × 10^{11} cm^{−2}\). For \(\rm V_G = 1.3 \ V\), the inversion carrier density is \(\rm 4 × 10^{11} cm^{−2}\). What is the value of the inversion carrier density for \(\rm V_G = 1.8 \ V\)?

Consider a region of silicon devoid of electrons and holes, with an ionized donor density of \({\rm{N}}_{\rm{d}}^ + = {10^{17}}{\rm{\;c}}{{\rm{m}}^{ - 3}}.\) The electric field at x = 0 is 0V/cm  and the electric field at x = L is 50 kV/cm in the positive x-direction. Assume that the electric field is zero in the y and z directions at all points.

Given \(\rm q = 1.6 × 10^{−19}\) coulomb, \(\rm \epsilon_o = 8.85 × 10^{−14} F/cm, \epsilon_r = 11.7\) for silicon, the value of \(\rm L( in \ nm)\) is ________.

Consider a long-channel NMOS transistor with source and body connected together. Assume that the electron mobility is independent of 𝑉_𝐺𝑆 and 𝑉_𝐷𝑆. Given, g_m = 0.5 𝜇A/V for 𝑉_𝐷𝑆 = 50 mV and 𝑉_𝐺𝑆 = 2 V,

g_d = 8 𝜇A/V for 𝑉_𝐺𝑆 = 2 V and 𝑉_𝐷𝑆 = 0 V,

Where \({{\rm{g}}_{\rm{m}}} = \frac{{\partial {{\rm{I}}_{\rm{D}}}}}{{\partial {{\rm{V}}_{{\rm{GS}}}}}}\)  and \({{\rm{g}}_{\rm{d}}} = \frac{{\partial {{\rm{I}}_{\rm{D}}}}}{{\partial {{\rm{V}}_{{\rm{DS}}}}}}\) 

The threshold voltage (in volts) of the transistor is ________.

The figure shows a half-wave rectifier with a 475 𝜇F filter capacitor. The load draws a constant current 𝐼_𝑂 = 1 A from the rectifier. The figure also shows the input voltage 𝑉_𝑖, the output voltage 𝑉_𝐶 and the peak-to-peak voltage ripple 𝑢 on 𝑉_𝐶. The input voltage 𝑉_𝑖 is a triangle-wave with an amplitude of 10 V and a period of 1 ms.

The value of the ripple 𝑢 (in volts) is ________

In the opamp circuit shown, the Zener diodes \(\rm Z_1\) and \(\rm Z_2\) clamp the output voltage \(\rm V_o\) to \(\rm +5 \ V\) or \(\rm −5 \ V\). The switch S is initially closed and is opened at time t = 0.

The time \(\rm t = t_1\) (in seconds) at which \(\rm V_o\) changes state is ________.

An opamp has a finite open-loop voltage gain of 100. Its input offset voltage V_ios (= +5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects. V_input is 25 mV.

The output voltage (in millivolts) is _________.

In an N bit flash ADC, the analog voltage is fed simultaneously to 2^𝑁 − 1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source V_in (whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF.

The input must settle to an accuracy of 1/2 LSB even for a full-scale input change for proper conversion. Assume that the time taken by the thermometer to the binary encoder is negligible.

If the flash ADC has 8-bit resolution, which one of the following alternatives is closest to the maximum sampling rate?

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X,

Y and Z, is shown in the figure.

Which one of the following statements is correct?

In the feedback system shown below  \(\rm G(s)=\frac{1}{{\left( {{{\rm{s}}^2} + 2{\rm{s}}} \right)}}\)

The step response of the closed-loop system should have a minimum settling time and have no overshoot.

The required value of gain 𝑘 to achieve this is ________

In the feedback system shown below  \(\rm G(s)=\frac{1}{{\left( {{\rm{s}} + 1} \right)\left( {{\rm{s}} + 2} \right)\left( {{\rm{s}} + 3} \right)}}\):

The positive value of 𝑘 for which the gain margin of the loop is exactly 0 dB and the phase margin of the loop is exactly zero degrees is ________.

The asymptotic Bode phase plot of \(\rm G(s)=\frac{{\rm{K}}}{{\left( {{\rm{s}} + 0.1} \right)\left( {{\rm{s}} + 10} \right)\left( {{\rm{s}} + {{\rm{p}}_1}} \right)}}\),  with K and 𝑝₁ both positive, is shown below.

The value of 𝑝₁ is ________.

An information source generates a binary sequence {𝛼_𝑛}. 𝛼_𝑛 can take one of the two possible values −1 and +1 with equal probability and are statistically independent and identically distributed. This sequence is precoded to obtain another sequence {𝛽_𝑛}, as \(\rm 𝛽_𝑛 = 𝛼_𝑛 + 𝑘 𝛼_{𝑛−3}\) . The sequence {𝛽_𝑛} is used to modulate a pulse \(\rm X(t)\) to generate the baseband signal

\({\rm{X}}\left( {\rm{t}} \right) = \mathop \sum \limits_{\rm{n= - \infty}}^\infty {\rm{\;\beta_ng}}\left( {{\rm{t}} - {\rm{nT}}} \right),\) where \({\rm{g}}\left( {\rm{t}} \right) = \left\{ {\begin{array}{*{20}{c}} {1,}&{0 \le {\rm{t}} \le {\rm{T}}}\\ {0,}&{{\rm{othervise}}.} \end{array}} \right.\)

A binary communication system makes use of the symbols “zero” and “one”. There are channel errors. Consider the following events:

𝑥₀ : a "zero" is transmitted

𝑥₁ : a "one" is transmitted

𝑦₀ : a "zero" is received

𝑦₁ : a "one" is received

The following probabilities are given:

\(\rm P(x_0) =\frac{1}{2},{\rm{\;P}}\left( {{{\rm{y}}_0}{\rm{|}}{{\rm{x}}_0}} \right) = \frac{3}{4}\ and\;p\left( {{y_0}{\rm{|}}{x_1}} \right) = \frac{1}{2}.\).

The information in bits that you obtain when you learn which symbol has been received (while you know that a “zero” has been transmitted) is ________

The parallel-plate capacitor shown in the figure has movable plates. The capacitor is charged so that the energy stored in it is 𝐸 when the plate separation is 𝑑. The capacitor is then isolated electrically and the plates are moved such that the plate separation becomes 2𝑑.

At this new plate separation, what is the energy stored in the capacitor, neglecting fringing effects?

A lossless microstrip transmission line consists of a trace of width 𝑤. It is drawn over a practically infinite ground plane and is separated by a dielectric slab of thickness 𝑡 and relative permittivity 𝜀_𝑟 > 1. The inductance per unit length and the characteristic impedance of this line are 𝐿 and 𝑍₀, respectively.

Which one of the following inequalities is always satisfied?

A microwave circuit consisting of lossless transmission lines T₁ and T₂ is shown in the figure. The plot shows the magnitude of the input reflection coefficient Γ as a function of frequency 𝑓. The phase velocity of the signal in the transmission lines is 2 × 10⁸ m/s.

The length 𝐿 (in meters) of T₂ is ________

A positive charge \(\rm q\) is placed at \(\rm x = 0\) between two infinite metal plates placed at \(\rm x = −d\) and at \(\rm x = +d\) respectively. The metal plates lie in the yz plane.

The charge is at rest at \(\rm t=0\), when a voltage \(\rm +V\) is applied to the plate at \(\rm – d\) and voltage \(\rm −V\) is applied to the plate at \(\rm x = +d\). Assume that the quantity of the charge \(\rm q\) is small enough that it does not perturb the field set up by the metal plates. The time that the charge \(\rm q\) takes to reach the right plate is proportional to